This invention relates to a non-retriggerable one-shot circuit.
One form of non-return-to-zero (NRZ) data coding is known as biphase coding. In biphase coding, a signal epoch is divided into time slots by a clock, and one source data bit occupies a single time slot. Each source data bit may be represented by a two-cell doublet. Each coding doublet begins, and therefore also ends, with a transition. A source data bit one generates a transition between the two cells of the doublet, whereas a source data bit zero does not. Thus, a source data bit zero is represented either as the doublet zero zero or the doublet one one, while a source data bit one is represented either by the doublet one zero or the doublet zero one.
In order to recover data from a biphase coded signal, it is necessary first to extract clock information from the signal. A conventional circuit for extracting clock information from a biphase coded signal is shown in FIG. 1. The biphase signal (FIG. 1, waveform A) is first differentiated and rectified, by applying the biphase signal and a delayed version thereof to respective inputs of an exclusive OR gate 2, so as to produce a signal (waveform B) that has one pulse for each transition of the biphase coded signal. The resulting pulse train is applied to a non-retriggerable one-shot 4 having a period equal to approximately 75% of the clock period. On the second transition of the first source data bit zero, the one-shot is set and its output (waveform C) remains high for 75% of the next clock period. If the next source data bit is also zero, the one-shot is set by the pulse that corresponds to the transition at the end of that bit, and if the next source data bit is one, the one-shot filters out the pulse that occurs between the two cells of the doublet and is set by the pulse corresponding to the transition at the end of that source data bit. The output of the one-shot is therefore a pulse train at the clock frequency and having a 75% duty cycle.
The output of the clock extraction circuit may be applied to the phase detector of a phase locked loop, to control operation of a voltage-controlled oscillator whose output constitutes the extracted clock signal and is applied to a data recovery circuit, such as a flip-flop.
The Audio Engineering Society/European Broadcasting Union datastream for digital audio data consists of a biphase coded signal in which each audio sample is represented by a subframe containing 32 time slots. The first four time slots of the subframe constitute a preamble containing at least one occurrence of the three cell sequence zero zero zero or one one one. However, so long as the time constant of the loop filter of the phase locked loop exceeds the duration of the preamble, this brief departure from the biphase coding rules does not disturb operation of the phase locked loop to such an extent as to prevent accurate recovery of data.
The Audio Engineering Society and European Broadcasting Union standards do not prescribe the clock frequency of the biphase coded signal used for the digital audio datastream. In different applications, clock frequencies ranging from 28 kHz to 54 kHz are employed, and this wide range in frequency can cause problems in clock extraction and data recovery. For example, a switch may be connected to select from multiple AES/EBU signal sources having different clock frequencies, but the clock extraction technique described with reference to FIG. 1 cannot be used to extract clock information reliably from the selected signal because a conventional non-retriggerable one-shot, having a fixed period, cannot be used to extract clock information in the manner described with reference to FIG. 1 unless the clock frequency of the biphase coded signal lies within a fairly narrow range.